As design rules shrink for MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, there is a need to improve the reliability and performance of n-type (hereafter called NMOS) transistors. One particular problem with devices having a channel length smaller than about 1 micron is referred to as a reverse narrow width effect in which threshold voltage decreases as the width of a shallow trench isolation (STI) feature that separates active areas decreases. As a result, the NMOS transistor performance and reliability are degraded.
A conventional process for fabricating a NMOS transistor involves forming a pad oxide on a substrate and depositing a silicon nitride cap layer on the pad oxide. A lithography and plasma etch process is used to form a shallow trench in the substrate. After an oxide liner is grown on the sidewalls and bottom of the trench, a dielectric material is deposited to fill the trench. The dielectric material is made coplanar with the nitride layer by employing a planarization process. The nitride and pad oxide layers are usually removed with a wet etch that leaves a recess in the top coners of the STI feature. Subsequent steps involve formation of a gate oxide and formation of a gate layer on the gate oxide. The gate layer which may be polysilicon or a similar material often fills the recess at the top corners of the STI structure. The presence of this conducting material can induce a local electric field below the corners of the gate oxide in the final device which leads to a lower threshold voltage (Vt) and higher leakage current in the NMOS transistor. Therefore, a method is needed to reduce the effect of the localized electric field adjacent to the top corners of the STI structure in order to improve device performance and reliability.
A shallow trench is also formed during the fabrication of a DRAM capacitor in U.S. Pat. No. 6,162,679. Here a conformal conductive layer is formed in a trench and a photoresist layer is coated on the conductive layer and etched back in the trench to protect a portion of the conductive layer while the exposed conductive layer is removed by a second etch step.
One method to reduce the reverse narrow width effect is described in U.S. Pat. No. 5,960,276 where a boron implant is performed on the sidewalls of the etched trench before an insulating material fills the STI feature. However, P+ to P well isolation is expected to be degraded due to the boron implant compensating the N well at the STI sidewall. Similarly, N+ to P well junction leakage will increase due to the boron implant increasing the P well implant concentration at the STI sidewall.
In related art found in U.S. Pat. No. 6,228,726, a boron implant is used to dope a region under an open trench to improve latchup immunity and to increase the N+ to N well and P+ to P well isolation. A method of forming a boron doped silicon sidewall in a trench structure is described in U.S. Pat. No. 5,296,392 and involves a CVD process with dichlorosilane as the silicon source gas and diborane as the source of the boron dopant.
In U.S. Pat. No. 6,277,697, a tilted boron implant is performed through a pad oxide into a substrate. A trench is etched into the substrate and leaves a pocket of boron dopant in the substrate adjacent to the upper corners of the STI structure. After the poly gate is formed, the doped region mitigates the influence of the local intensified electric field caused by polysilicon filling the etched recess at the top corners of the STI structure. Since the implant is performed prior to high temperature oxidation and anneal steps in the trench fabrication, a considerable amount of dopant is likely to be lost from the implanted regions.
Because of the tendency for boron to diffuse away from its implanted location during subsequent thermal cycles and thereby cause a depletion of dopant in desired regions, a reverse narrow channel effect (RNCE) is likely to occur. The RNCE is reduced in U.S. Pat. No. 6,245,639 by a large angle N ion implant into sidewalls of a trench which blocks B ions from migrating to an STI/well interface.
A method is described in U.S. Pat. No. 6,331,458 for implanting indium ions in an active region between two field oxide regions formed by a LOCOS method. The method teaches that the lower mobility of indium compared with boron in a substrate results in a lower threshold voltage skew but does not address the influence of the etched recess in an STI structure on reverse narrow width effect in an NMOS transistor which may also be referred to as Vt roll-off. Furthermore, the method does not allow for a higher dopant concentration in a region of the substrate adjacent to the STI corners and a lower concentration in other parts of the active region.
An indium ion implant is also employed in U.S. Pat. No. 6,504,219 in which the indium ions are vertically implanted into the bottom of an STI trench to strengthen a p-well and provide punchthrough protection. However, the method does not address the problem of Vt roll-off caused by an etched recess at top corners of the STI structure.
Therefore, a method is desirable for fabricating an NMOS transistor having an STI structure that enables the flexibility of placing a high concentration of dopant selectively in the active region adjacent to top corners of an STI structure. A preferred process does not degrade the isolation or junction performance and is adjustable to permit various degrees of threshold voltage improvement.